In order to take advantage of circuits that comply with lower voltage standards (e.g., 1.0V, 1.5V, 1.8V, 2.5V, 3.3V, etc.) in memories (e.g., DRAMs, SPAMs, flash, etc.) that may be implemented in higher voltage applications or environments (e.g., 1.5V, 1.8V, 2.5V, 3.3V, 5V, etc.), an on-chip voltage converter that delivers a stable low-voltage "internal" Vcc from an externally provided high-voltage supply is generally required.
The easiest driver to configure is an N-MOS transistor biased in a source-follower configuration. Although very attractive for its simplicity, such an architecture presents several drawbacks.
First, in order to deliver 3.3V at an output, the gate of the source-follower must be kept at a higher voltage (e.g., 4.3V) in a process technology optimized for higher voltage operation (e.g., at or about 5 V). Since a bandgap reference circuit delivers relatively low voltage (e.g., only 1.5V for circuitry made in 5V-optimized process technology), an operational amplifier may be required between the output of the bandgap and the gate of the source-follower for reliable operation. The operational amplifier complicates the architecture, increases area and power consumption and, most importantly, introduces additional power supply noise to the circuit. The above example voltages may be accurate for a CMOS technology using a 5 volt power supply. Other technologies and power supplies may have different voltages.
Secondly, with 4.3V at its gate and 3.3V at its source, the overdrive voltage of the source-follower is limited. Therefore, in order to deliver 200 mA of current, the transistor must be made rather wide (e.g., about 8000 .mu.m). When taken together with the operational amplifier, this results in a large circuit.
Thirdly, the absence of a stabilizing scheme leaves the source-follower very sensitive to noise.
Another conventional architecture often utilized is the stabilized driver shown in FIG. 1. An operational amplifier A2 provides negative feedback to the driving P-MOS device PD. When the chip load sinks current, the output VCCI tends to decrease, which in turn, decreases the input difference of the amplifier A2. As a result, a voltage COUT decreases, which increases the overdrive voltage of the P-MOS driver PD. Such an overdrive voltage provides more current to the load, which returns VCCI to its original value. The stabilizing effect of the feedback results in a higher immunity to noise and power supply variations. The circuit of FIG. 1 may work well when the load current varies smoothly within a limited range and the load capacitance is not too large.
Under these assumptions, the feedback has enough time to react to the variation in load current. Unfortunately, such assumptions are not necessarily valid for low voltage operation of a memory device. Not only may the chip capacitance be very large relative to the current-providing capabilities on the chip (e.g., 3 nF for currents of up to about 200 mA for a 1M SRAM), but also the load current switches abruptly from hundreds of nA to over 200 mA when the chip is enabled and addresses and/or data signals begin to toggle.
Under these extreme conditions, it becomes very difficult to design an amplifier with enough bandwidth to provide a reliable and/or stable output in a time period sufficiently short to comply with chip and/or system performance requirements. Preliminary simulations have shown that, given the nature of the load, a two-stage (or even a three-stage) amplifier may be needed in order to obtain modern-day gain and bandwidth performance. However, a two-stage amplifier requires a compensation network to achieve 60-70 degrees of phase margin needed to ensure stability. Such a compensation network not only takes a considerable amount of silicon area (for a 3 nF load capacitance, a compensation capacitance of 300 pF is needed), but it. also slows down the overall response of the amplifier, limiting the efficiency of the feedback loop.
The possibility of designing the amplifier without a compensation network has been studied as well. In this case, the load capacitance would determine the dominant pole of the circuit. Although this solution seems attractive in terms of area and power consumption, it shows stability problems due to the fact that the position of the dominant pole is determined not only by the load capacitance but also by the load current (I.sub.load) since Gm (the gain) of the P-MOS driver is a function of I.sub.load. Load current variations of several orders of magnitude imply a dominant pole that moves significantly during operation, degrading the phase margin and the stability of the circuit.
Ishibashi et al. have proposed implementing the driver as part of a single-stage amplifier in buffer configuration as shown in FIG. 2. Although an improvement over the circuit of FIG. 1 in terms of stability, the circuit presents two major drawbacks. First, the circuit takes a considerable amount of area. Second, the circuit suffers severely from power supply noise. In fact, the power supply rejection ratio (PSRR) of a single stage amplifier is intrinsically low. Also, the aspect ratio of the P-MOS active load is larger than the one of the N-MOS differential pair in order to obtain high current drive capability. This substantially amplifies the noise introduced by the power supply.